1. Field
Exemplary embodiments of the present invention relate to a data transfer circuit which receives and transfers data in the inside of a semiconductor chip, and a memory device including the data transfer circuit.
2. Description of the Related Art
As semiconductor related technologies are being advanced, operation speeds of semiconductor memory devices are becoming faster. A Synchronous Dynamic Random Access Memory (SDRAM) device operates in synchronization with an external clock. Recently, a Double Data Rate (DDR) SDRAM device is developed and used. The DDR SDRAM device is designed to have a high data transfer rate by synchronizing input/output data with a clock not only at a rising edge but also at a falling edge as well.
A DDR SDRAM device is advanced from DDR1 to DDR2 and DDR3. In case of DDR1, 2-bit prefetch is performed and the burst length (BL) of an input/output data is 2. In case of DDR2, 4-bit prefetch is performed and the burst length of an input/output data is 4. In case of DDR3, 8-bit prefetch is performed and the burst length of an input/output data is 8. Herein, the fact that the burst length is 8 means an 8-bit data synchronized with a clock is continuously inputted/outputted through one data input/output pad.
When a memory device performs a write operation of receiving and storing a data, it may take a certain time to transfer the data inputted from the outside to a memory cell region through an internal circuit and store the data in the capacitor of each memory cell. Therefore, a write command applied from the outside should be received at a minimum time interval, which is Column Address Strobe (CAS) to CAS Delay time tCCD. For example, when a DDR3 SDRAM device performs a write operation with BL8, the time interval between the write commands that may be applied consecutively has to be at least 4tCK or longer.
FIG. 1 is a block diagram illustrating a data transfer path in a conventional memory device. It is assumed that the memory device is a DDR3 SDRAM device.
Referring to FIG. 1, the conventional memory device includes a data input pad 101, a serial-to-parallel converter 103, a data transmission unit 105, and a memory cell region 107. The serial-to-parallel converter 103 convert data that are inputted in series through the data input pad 101 and a serial data line DIN into parallel data. The parallel data are provided to the data transfer 105 through parallel data lines DINP<0:7>. The data transmission unit 105 transfers the parallel data to global data buses GIO<0:7>. The memory cell region 107 stores the data transferred through the global data buses GIO<0:7>. Herein, FIG. 1 illustrates a structure between one data input pad 101 and the memory cell region 107, and the structure may be implemented as many as the number of data input pads in the inside of a memory device.
A DDR3 SDRAM device is basically designed to perform a BL8 operation, but it may also support a BL4 operation as well. This will be described hereafter with reference to FIGS. 2A and 2B.
FIG. 2A is a timing diagram of a BL8 write operation performed in the memory device of FIG. 1.
The timing diagram illustrates that a write command and a data inputted corresponding to the write command are applied at the same clock timing. However, it is just for the sake of convenience in description and in reality, a write command may be applied first and then a data corresponding to the write command may be inputted after a write latency time passes.
Referring to FIG. 2A, when the DDR3 SDRAM device performs a write operation, write commands WT1 and WT2 are applied at a time interval of 4tCK, and 8-bit serial data D0, D1, . . . , D7 and D8, D9, . . . , D15 which correspond to the write commands WT1 and WT2, respectively, are inputted to the serial data line DIN through the data input pad 101. The serial-to-parallel converter 103 converts the 8-bit serial data D0, D1, . . . , D7 and D8, D9, . . . , D15 into 8-bit parallel data D0˜D7 and D8˜D15 at every 4tCK and outputs them to 8 lines DINP<0:7>. The data transmission unit 105 latches the 8-bit parallel data D0˜D7 and D8˜D15 inputted through the parallel data lines DINP<0:7>, and transfers them to the global data buses GIO<0:7> at a timing when a transfer enable signal ENGIO is activated to a logic high level. The transfer enable signal ENGIO is activated at a time interval of 4tCK. Subsequently, the 8-bit parallel data D0˜D7 and D8˜D15 are transferred to the memory cell region 107 through the global data buses GIO<0:7> and stored in a selected bank (not shown).
FIG. 2B is a timing diagram of a BL4 write operation of the memory device shown in FIG. 1.
Referring to FIG. 2B, during a BL4 write operation of the DDR3 SDRAM device, 4-bit serial data D0, D1, D2, D3 and D4, D5, D6, D7 corresponding to the write commands WT1 and WT2, respectively, are inputted to the serial data line DIN through the data input pad 101. The serial-to-parallel converter 103 converts the 4-bit serial data D0, D1, D2, D3 and D4, D5, D6, D7 into 4-bit parallel data D0˜D3 and D4˜D7 at every 4tCK and outputs them to the lines DINP<0:7>. Herein, among the 8 lines DINP<0:7>, four of them may be used. The data transmission unit 105 latches the 4-bit parallel data D0˜D3 and D4˜D7 inputted through the parallel data lines DINP<0:7> and transfers them to the global data buses GIO<0:7> at a timing when a transfer enable signal ENGIO is activated to a logic high level. Herein, too, among the 8 lines DINP<0:7>, four lines for transferring the 4-bit parallel data may be used. The transfer enable signal ENGIO is activated at a time interval of 4tCK, just as in the BL8 operation. Subsequently, the 4-bit parallel data D0˜D3 and D4˜D7 are transferred to the memory cell region 107 through the global data buses GIO<0:7> and stored in a selected bank (not shown).
In order to acquire the same data transfer efficiency in the BL4 operation as in the BL8 operation, the write commands WT1 and WT2 should be applied at a time interval of 2tCK, which is half the time interval of the BL8 operation. However, storing a data in a memory cell actually takes more time than a predetermined physical time, and it may also take a certain time for the global data buses GIO<0:7> to normally transfer a data, because the global data buses GIO<0:7> has a parasitic capacitance and a parasitic resistance. Therefore, during the BL4 operation, the write commands WT1 and WT2 have to be applied at a time interval of at least tCCD, which may be 4tCK.
In short, since the write commands WT1 and WT2 should be applied at a time interval of 4tCK even in the BL4 operation in the conventional memory device, just as in the BL8 operation, no data may be inputted during 2tCK of the 4tCK. Therefore, the data transfer efficiency may be decreased by half, compared with the BL8 operation.